Random access memory (RAM) includes digital bit storage cells in an array of rows and columns. A RAM redundant integrated circuit is an integrated circuit or chip which includes a redundant RAM which is a RAM that contains redundant rows and/or columns of bit storage cells. The redundant rows or columns are used to replace rows or columns of the RAM that have failed under test. Thus, a chip found to have a failed row or column during test may be repaired by replacing the failed row or column with a good redundant row or column.
An exemplary RAM redundant integrated circuit production process may be described by a flow chart of steps depicted in FIG. 1. Block diagram schematics of FIGS. 2 and 3 exemplify present techniques for testing the RAM redundant integrated circuits. Referring to FIGS. 1-3, RAM redundant integrated circuit dies 10 are fabricated on a silicon wafer 12. Once the fabrication process is complete, the integrated circuit dies 10 of the wafer 12 may be coupled electrically to a tester unit 14 over test signal lines 16, for example. In step A1, each RAM of the dies 10 is tested at the wafer level. In step A2, if the tester unit 14 finds a failed row or column in a RAM, it may output programming data to a file which is read by a separate laser programmer 18 to perform the programming of the RAM.
Currently, RAM redundant integrated circuit dies include programmable fuses which may be blown to connect a redundant row or column of a RAM to replace a failed row or column. In step A2, programming is accomplished at the wafer level by the programmer 18 controlling a laser 20 to blow appropriate fuses of a die 10 with its laser beam 22 to replace each failed row (or column) of each RAM with a redundant row (or column). In step A3, each programmed die 10 may be sectioned from the wafer and disposed in an appropriate package 24. Input/output circuits of the die 10 are connected to corresponding pins 26 of the package 24 to form a RAM integrated circuit part.
Each packaged part 24 undergoes a burn in period in step A4 to screen out parts that may fail early. A typical burn in process may include disposing the part in a high temperature oven 30, the temperature of which being controlled by a temperature controller 32. During the burn in operation, high voltage signals may be applied to the pins 26 of the RAM part 24 by a tester-signal generator 40 via signal lines 34, connector 36 and leads 38. A typical burn in process may take approximately two hours, for example. However, it is understood that burn in times may vary widely depending on such factors as fabrication process, die area, and burn in voltage and temperature, for example. Some types of burn in ovens include electronic hardware for running vectors to test the RAM parts. Parts that fail burn in are usually parts that are found to consume too much current or to have a continuity error, such as a short or open circuit, for example. Such failed parts may not make it to a package test.
After burn in, the packaged parts 24 are retested by the tester 40 in step A5. If the part 24 passes the package test as determined by step A6, the part 24 is put in inventory for later shipment to a customer. Otherwise, if the part fails the test as determined by step A6, the part is scrapped. There is no procedure in the current production process to repair or reprogram the redundant RAM at the package level. Accordingly, if a row or column is determined to have failed at the package level, during burn in or retest, the entire packaged part is scrapped which reduces the overall production yield.